1. Field of the Invention
The present invention generally relates to partitioning integrated circuit designs and more particularly to a methodology that bases the partitioning upon the logical hierarchy of the integrated circuit design and that maintains the partitions within a desired size limit.
2. Description of the Related Art
Current integrated circuit designs have grown large enough to require partitioning to handle the data in parallel. Automatic fracturing in a matrix or grid like manner results in inefficient pieces of graphics data. This inefficiency propagates to subsequent processing. This invention addresses how to automatically and intelligently partition design data based on macros.